Volume : II, Issue : X, October - 2013

Multiple Error Correction Controlling

M. Venkataramanamma, U. Kalpana Reddy

Abstract :

Using a Field Programmable Gate Array (FPGA) reconfigurable chip the design and implementation of (31,k) binary BCH (Bose, Chaudhuri, and Hocquenghem) encoder is presented in this paper. Amongst the most important cyclic block codes BCH code is one. Designing on FPGA leads to a high calculation rate using parallelization (implementation is very fast), and it is easy to modify. BCH encoder has been designed and simulated using Xilinx–ISE 10.1 Web PACK and implemented in a xc3s700a–4fg484 FPGA. In this implementation, A 31 bit–size code word has been used. The BCH code encoders of (31, 21, 2), (31, 16, 3) and (31, 11, 5) have implemented on FPGA. The results show that the systems work quite well.

Keywords :

Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

M. Venkataramanamma, U. Kalpana Reddy / Multiple Error Correction Controlling / International Journal of Scientific Research, Vol.2, Issue.10 October 2013

Number of Downloads : 1238

References :