Volume : II, Issue : XII, December - 2013

Metaheuristic Approach for VLSI 3D–Floorplanning

Mr. Lalin L. Laudis, Mr. Amit Kumar Sinha

Abstract :

From the period of evolution of VLSI began; floor planning for the physical design was the most important problem to concern about. Modern three-dimensional (3D) chips are based on the fact that, the active devices are placed in multiple layer using 3D integration technologies. Though the 3D chips are latest, the growth and progress in the development are not up to the mark. The complex problem to be viewed in 3D VLSI design is the floorplanning part. The two Dimensional VLSI chips which are in application today also encountered the same floorplanning problem. In three dimensional VLSI chips, as the devices are placed in multiple layer, the placement of blocks play a vital role in the chip size. It seems to be a herculean task for the designers for placing the components in the proper place with efficient usage of available place. In this paper a solution to the modern 3D VLSI floor planning is proposed based on a a algorithm named simulated annealing. It is expected that the algorithm would work more efficiently in 3D VLSI chips as the same algorithm produced more optimal solutions for various benchmark problems in 2D VLSI floorplanning.

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Article: Download PDF   DOI : 10.36106/ijsr  

Cite This Article:

Mr. Lalin L. Laudis, Mr. Amit Kumar Sinha Metaheuristic Approach for VLSI 3D-Floorplanning International Journal of Scientific Research, Vol.II, Issue.XII December 2013

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