IMPLEMENTATION OF 16:1 MULTIPLEXER IN LOW POWER QUATERNARY LOGIC LOOK UP TABLE

P. Rama Krishna; J. Yashwanth Kumar

Volume : V, Issue : IV, April - 2016

IMPLEMENTATION OF 16:1 MULTIPLEXER IN LOW POWER QUATERNARY LOGIC LOOK UP TABLE

P. Rama Krishna, J. Yashwanth Kumar

Abstract :

<p>&nbsp;These Most of the chip area in FPGA is consumed by Lookup tables (LUT) and configurable routing switches. Reduction in power consumption can be achieved by scaling down interconnections through MVL. Closer levels in MVL reduces power required for level transition. By using Quaternary logic we can reduce the interconnections, as each circuit wire in quaternary logic can carry the same information as that of two wires in binary logic. In this paper, we design a low power look up table, based on quaternary logic and implement a 16:1 multiplexer using it. Cadence virtuoso GPDK 180nm technology is used to design the look up table in standard CMOS with power consumption of 88&micro;W at 500 MHz frequency.</p>