FPGA IMPLEMENTATION OF DUAL KEY BASED AES ENCRYPTION AND DECRYPTION WITH KEY BASED S-BOX GENERATION

Yada Indumathi; M.Shiva Kumar

Volume : VI, Issue : III, March - 2017

FPGA IMPLEMENTATION OF DUAL KEY BASED AES ENCRYPTION AND DECRYPTION WITH KEY BASED S-BOX GENERATION

Yada Indumathi, M. Shiva Kumar

Abstract :

AES is mostly and approved algorithm in cryptography. Cryptography is an important role in secure network. The important secure network block cipher is Rijndael cipher and also known as AES. The advanced research is going in the field of cryptography. Finally a most of changes have been proposed on this AES algorithm. Static S-Boxes in this algorithm are implemented using look up tables in this they did not vary in input key or input text so this technique is easy to reverse engineering. This consumes a lot of space for the look up table. Another disadvantage of AES is that it works with a single key. So it is essential to generate S-Bytes at simulation time. It is beneficial if the S-byte generated during run time varies with the input key. In this paper, a new theory of AES is proposed, dual key AES with Key Based S-Box Generation. In this increases the level of security by using high usage of resources and less power with high performance. In this, the architecture of the algorithm for optimal FPGA implementation using Verilog HDL code using Vivado 14.3 and implemented on Zynq Board (FPGA).