Volume : VI, Issue : III, March - 2017

FPGA IMPLEMENTATION OF 32-BIT VEDIC MULTIPLIER AND SQUARE ARCHITECTURES

T. Sravanthi Devi, A. Madhu Sudhan

Abstract :

 The Main Objective of the Project is to Design Vedic Mathematics based “ALU” using Reversibility Technique for DSP Applications. In Order to Reduce Delay, Area, Complexity, power consumption, Improve the High speed. The Proposed “ALU” is Coded in Verilog, Synthesized and Simulated using Xilinx ISE Tool. Reversibility is used to reduce area, complexity. And the multiplication is done by using Vedic Multiplier; Vedic multiplier is used to increase the speed. We are Designing our Architecture in Verilog HDL code and also simulated using Vivado 2015.2 Tool and Hardware Implementation on ZYNQ Board(FPGA).The Project functionality input and output to the system is digital data. And the process expected to be done in the system is Arithmetic and logical operations and Multiplication process. The specifications of “ALU” are two 4bits digital data input bit size and 8bit digital data output bit size. 

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Article: Download PDF    DOI : https://www.doi.org/10.36106/gjra  

Cite This Article:

FPGA IMPLEMENTATION OF 32-BIT VEDIC MULTIPLIER AND SQUARE ARCHITECTURES, T.SRAVANTHI DEVI, A.MADHU SUDHAN GLOBAL JOURNAL FOR RESEARCH ANALYSIS : Volume-6 | Issue-3 | March-2017

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