FOLIAR ARCHITECTURE OF INDIAN Spilanthes Jacq.: MEMBERS OF THE TRIBE HELIANTHEAE OF SUB FAMILY ASTEROIDEAE

N.K.MAITRA; S. K. MUKHERJEE

Volume : VI, Issue : III, March - 2017

FOLIAR ARCHITECTURE OF INDIAN Spilanthes Jacq.: MEMBERS OF THE TRIBE HELIANTHEAE OF SUB FAMILY ASTEROIDEAE

N. K. Maitra, S. K. Mukherjee

Abstract :

The processor speed of operation is depends on the adder. In digital world the processor operation is main design consideration is high performance adder with less area and small power consumption is important for design a digital adder. The proposed carry select adder is designed for the advanced processors. This paper proposes the fpga implementation high performance carry select adder without using the multiplexer for the final selection of the sum. The approach for design a CSA we implemented by using the high speed parallel prefix adder and then first finding zero logic. By removing the multiplexer in the final stage as a result the area as well as power consumption is reduce. For the selection of the high speed carry generator we use the Kogge stone parallel prefix adder. It will generate the fast carry for intermediate stages of the adder. The adder is designed by using the verilog HDL in VIVADO IDE and implemented on the Zynq Board. The proposed carry select adder is consume less power and occupies less area compared to conventional carry select adder with ripple carry adder. < clear="all" style="page-eak-before:always;mso-eak-type:section-eak" />