Volume : VII, Issue : I, January - 2018

A Bus Encoding Technique for Minimizing Delay in VLSI Interconnects

Tanu Verma

Abstract :

 

In a typical bus system of NOC, crosstalk can affect signal delays by changing the times at which signal transitions occur. Hence, Delay reduction is main objective of our current research work. This paper develops a novel technique, in which inter-wire crosstalk considers sufficiently and reduces the delay due to coupling transition approximately up to 13% - 13.63% for 8 bit, 16 bit, 32 bit and 64 bit wide data bus with an additional area penalty. The effectiveness of coding method has been tested using MATLAB. Transmission results are tested on bus of network on chip which is simulated on Xilinx and implemented on FPGA.

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Article: Download PDF    DOI : https://www.doi.org/10.36106/gjra  

Cite This Article:

Tanu Verma, A Bus Encoding Technique for Minimizing Delay in VLSI Interconnects, GLOBAL JOURNAL FOR RESEARCH ANALYSIS : VOLUME-7, ISSUE-1, JANUARY-2018

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